Method of protecting semiconductor areas while exposing a gate

US6562713B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Michael P. Belyansky · Hopewell Junction, US
• Omer H. Dokumaci · Wappingers Falls, US
• Bruce B. Doris · Brewster, US
• Hussein I. Hanafi · Berkeley Heights, US

Key dates

• Filing date: Feb 19, 2002
• Grant date: May 13, 2003
• Expiry date: Feb 19, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Disclosed is a method of protecting semiconductor areas while exposing a gate for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma layer of a silicon compound, selected from the group silicon oxide and silicon nitride, in a manner effective in leaving an upper surface of said gate exposed. Also disclosed is a method of processing short gates while protecting long gates on a semiconductor surface, the method comprising depositing a planarizing layer of a silicon compound, selected from the group silicon nitride and silicon oxide, up to substantially the same height as said gates, and processing said semiconductor surface.