Patent · US Expired

Advanced bit fail map compression with fail signature analysis

US6564346B1 · kind B1 · utility

22Cited by

4References

33Claims

0Family size

Assignee

Infineon Technologies Richmond, LP · US

Inventors

Joerg Vollrath · Richmond, US
Ulf Lederer · Dresden, DE
Peter Oswald · Bernhaupten, DE
Thomas Hladschik · Matosinhos, PT
Zschunke Andreas · Dresden, DE
Rausch Harold · Radeberg, DE

Key dates

Filing date	Dec 7, 1999
Grant date	May 13, 2003
Priority date	—
Expiry date	Dec 7, 2019

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/56
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices and transferring failure information to display a compressed bit map by designating areas of the bit map for corresponding failure locations on the semiconductor device. Failure classification is provided by designating shapes and dimensions of fail areas in the designated areas of the bit map such that the fail area shapes and dimensions indicate a fail type.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.