Sidewall protection in fabrication of integrated circuits

US6566196B1 · kind B1 · utility

Assignee

• MOSEL VITELIC INC. · TW

Inventors

• Barbara Haselden · Cupertino, US
• Chia-Shun Hsiao · Cupertino, US
• Chunchieh Huang · Beijing, CN
• Jin Ho Kim · Seojong-myeon, KR
• Chung Wai Leung · Orlando, US
• Kuei-Chang Tsai · Cupertino, US

Key dates

• Filing date: May 15, 2002
• Grant date: May 20, 2003
• Expiry date: May 15, 2022

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/954

Abstract

In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.