Inspection of circuit patterns for defects and analysis of defects using a charged particle beam
US6566654B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Oct 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/3174
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention is intended to detect defects in a circuit pattern formed on a semiconductor wafer by a circuit pattern forming process, to facilitates the extraction and observation of the defects, to improve the accuracy of analysis of the causes of the defects, and to determine the causes of the defects and to take measures to eliminate the causes of the defects in a greatly reduced time after the formation of the defects. A method of inspecting a circuit pattern for defects and analyzing defects, comprising locating a defect in a circuit pattern formed on a wafer by using an electron beam, specifying a chip having the defect on the basis of position data on the defect, cutting out the chip from the semiconductor wafer, thinning a portion of the chip to form a thin portion, and observing the thin portion of the chip under a transmission electron microscope to determine the causes of the defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.