Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6566699B2 · kind B2 · utility
90Cited by
101References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Aug 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of enhancing erasure of a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer includes programming the cell to minimize the width of a trapping region within the charge trapping layer by reading with a minimum voltage on the gate in a direction opposite that of programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.