Memory device and method for reliably reading multi-bit data from a write-many memory cell
US6567304B1 · kind B1 · utility
16Cited by
14References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 9, 2002 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The preferred embodiments described herein provide a memory device and method for reliably reading multi-bit data from a write-many memory cell. In one preferred embodiment, a non-volatile, write-many memory cell operative to store multiple bits is provided, and the number of program/erase cycles to the write-many memory cell is limited. Limiting the number of program/erase cycles increases the probability that multi-bit data will be correctly read from the memory cell. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.