Methods for forming co-axial interconnect lines in a CMOS process for high speed applications

US6569757B1 · kind B1 · utility

Assignee

• Philips Electronics North America Corporation · US

Inventors

• Milind Weling · San Jose, US
• Subhas Bothra · Fremont, US
• Calvin T. Gabriel · Cupertino, US
• Michael N. Misheloff · Dublin, US

Key dates

• Filing date: Oct 28, 1999
• Grant date: May 27, 2003
• Expiry date: Oct 28, 2019

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T29/49123
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.