2Bit/cell architecture for floating gate flash memory product and associated method

US6570211B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Yue-Song He · San Jose, US
• Richard Fastow · Cupertino, US
• Zheng Wei · Dongguan, CN

Key dates

• Filing date: Jun 26, 2002
• Grant date: May 27, 2003
• Expiry date: Jun 26, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

The invention relates to a flash memory devices and a method associated therewith in which combined source/drain regions are shared by more than two memory cells. For example, source/drain regions can be shared by four adjacent memory cells. Such sharing can be accomplished by providing memory cells along main branches of word lines and additional memory cells along dead end branches extending off the main branches. Another aspect of the invention relates to a flash memory device wherein the memory cells are arrayed and a first portion of the memory cells are read with source and drain regions sharing a row of the array and a second portion of the memory cells are read with source and drain regions sharing a column of the array.