Programming with floating source for low power, low leakage and high density flash memory devices
US6570787B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2002 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Apr 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.