Load for non-volatile memory drain bias
US6570789B2 · kind B2 · utility
1Cited by
28References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.