Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips
US6571374B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2000 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Feb 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EQUATE property is introduced into the layout cell data for a layout design to identify the schematic to which the layout design corresponds. Rather than exploding the layout cell up to the next level for flat checking because the equivalent schematic is not known, the layout cell instances may then be checked hierarchically, with one instance checked internally for compliance with design rules and the like while the remaining instances are merely checked for proper connection to neighboring cells. New layout cell designs may therefore be created as the need arises during layout without requiring schematic checking tools to be rerun.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.