Circuit configuration for enabling a clock signal in a manner dependent on an enable signal
US6573754B2 · kind B2 · utility
38Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2002 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | May 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The second signal path contains an RS flip-flop, upstream of which NAND gates are connected, which, for their part, are connected via different inverters to the input terminals for the clock signal and the enable signal, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.