Depletion mode ferroelectric memory device and method of writing to and reading from the same
US6574131B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Jul 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Such memory cells find use in non-volatile memory devices as well as other electronic systems having non-volatile memory storage. Various embodiments are described having ferroelectric transistors formed on a semiconductor layer overlying a bit line. By forming the transistors on this elevated semiconductor layer, the underlying substrate is usable for other components of a memory device, such as sensing devices and decoder circuits, thus facilitating higher-density devices. Because the transistors display bulk transport characteristics, they can be fabricated on polysilicon as the semiconductor layer despite relatively poor Si—SiO2 interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.