Software prefetch system and method for predetermining amount of streamed data
US6574712B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Apr 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.