Darc layer for MIM process integration
US6576526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2001 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Jul 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.