Daniel Yen
22Patents
10h-index
33Co-inventors
71Inventor score
Filing activity: Apr 19, 1990 → Jan 12, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5003062A | Semiconductor planarization process for submicron devices | Emerging Cross-Sectional Technologies | 121 | Expired |
| US6632712B1 | Method of fabricating variable length vertical transistors | Electricity | 49 | Expired |
| US6576526B2 | Darc layer for MIM process integration | Electricity | 47 | Expired |
| US5883001A | Integrated circuit passivation process and structure | Emerging Cross-Sectional Technologies | 33 | Expired |
| US6468851B1 | Method of fabricating CMOS device with dual gate electrode | Electricity | 24 | Expired |
| US5106787A | Method for high vacuum controlled ramping curing furnace for SOG planarization | Electricity | 23 | Expired |
| US6630380B1 | Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) | Electricity | 22 | Expired |
| US6004622A | Spin-on-glass process with controlled environment | Electricity | 15 | Expired |
| US5716673A | Spin-on-glass process with controlled environment | Electricity | 13 | Expired |
| US7067869B2 | Adjustable 3D capacitor | Electricity | 12 | Expired |
| US6429109B1 | Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate | Electricity | 10 | Expired |
| US6610575B1 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Electricity | 8 | Expired |
| US6841441B2 | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing | Electricity | 8 | Expired |
| US6664153B2 | Method to fabricate a single gate with dual work-functions | Electricity | 7 | Expired |
| US6713335B2 | Method of self-aligning a damascene gate structure to isolation regions | Electricity | 7 | Expired |
| US5174043A | Machine and method for high vacuum controlled ramping curing furnace for sog planarization | Electricity | 5 | Expired |
| US6610604B1 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Electricity | 5 | Expired |
| US6689643B2 | Adjustable 3D capacitor | Electricity | 3 | Expired |
| US6544848B1 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers | Electricity | 3 | Expired |
| US6803305B2 | Method for forming a via in a damascene process | Electricity | 2 | Expired |
| US6686279B2 | Method for reducing gouging during via formation | Electricity | 2 | Expired |
| US6828082B2 | Method to pattern small features by using a re-flowable hard mask | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.