‘Via first’ dual damascene process for copper metallization
US6576550B1 · kind B1 · utility
19Cited by
17References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Nov 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The process of filling the vias and trenches involves use of a silicon nitride film as an etch stop and the filling of the vias with an anti-reflection coating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.