Self-aligned nitride pattern for improved process window
US6576944B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2000 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Apr 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
Abstract
A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first conductive material is recessed to a level below a top surface of the substrate in the trench. A dielectric layer is conformally deposited in contact with the first conductive material in the trench and in contact with sidewalls of the trench. A hole is formed in the dielectric layer to expose the first conductive layer, and the hole is filled with a conductive material. A gate stack is formed over the trench such that an electrical connection is made to the first conductive layer in the trench by employing the conductive material through the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.