Semiconductor device comprising capacitor cells, bit lines, word lines, and MOS transistors in a memory cell area over a semiconductor substrate
US6576946B1 · kind B1 · utility
13Cited by
5References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 20, 1999 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Jul 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.