Chip size semiconductor packages with stacked dies
US6577013B1 · kind B1 · utility
334Cited by
37References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2000 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Oct 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Chip-size semiconductor packages (“CSPs”) containing multiple stacked dies are disclosed. The dies are mounted on one another in a stack such that corresponding ones of the vias in the respective dies are coaxially aligned. An electrically conductive wire or pin is in each set of aligned vias and soldered to corresponding ones of the terminal pads. The pins include portions protruding from the stack of dies that serve as input-output terminals of the package. Heat spreaders can be interleaved between the stacked dies to enhance heat dissipation from the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.