Method of burning in an integrated circuit chip package
US6577146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2001 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Apr 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2863
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An improved method of burn-in of I/C chips is provided wherein, at the beginning of the burn-in process, the thermal resistance between the heatsink and the chip is measured at reduced power, the maximum allowable thermal resistance between the chip and heatsink interface is calculated and compared to the actual thermal resistance of the interface. If the actual thermal resistance measured at the interface between the heatsink and the chip package is greater than the maximum allowable calculated thermal resistance, then the corrective action is initiated in order to prevent damage to the I/C chip during burn-in or increase efficient use of the test sites.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.