Process for producing a resistor in an integrated circuit and corresponding integrated static random access memory device having four transistors and two resistors
US6580130B1 · kind B1 · utility
7Cited by
15References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated static random access memory device includes four transistors and two resistors defining a memory cell. The four transistors are in a semiconductor substrate and are mutually interconnected by a local interconnect layer. The local interconnect layer is under a first metal level and a portion of the local interconnect layer defines above the substrate a base metal level. The two resistors extend in contact with a portion of the local interconnect layer between the base metal level and the first metal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.