Double LDD devices for improved DRAM refresh
US6580149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Jan 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.