Method of erasing nonvolatile tunneling injector memory cell
US6580642B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Jun 17, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a non volatile memory cell having a floating gate disposed over and insulated from a semiconductor substrate by a gate insulation layer, a grid electrode disposed over and insulated from the floating gate, and an injector electrode disposed over and insulated from the grid electrode. The substrate includes source and drain regions with a channel region defined therebetween. The method includes the steps of applying a first voltage to the substrate, and applying a second voltage to the grid electrode and to the injector electrode, wherein the first voltage is sufficiently more positive with respect to the second voltage to induce electrons on the floating gate to tunnel through the gate insulation layer to the substrate via Fowler-Nordheim tunneling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.