Method for forming damascene dual gate for improved oxide uniformity and control

US6583011B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Li-Qun Xia · Santa Clara, US
• Gao Feng · Singapore, SG
• Yong Meng Lee · Singapore, SG

Key dates

• Filing date: Jan 11, 2000
• Grant date: Jun 24, 2003
• Expiry date: Jan 11, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981

Abstract

A method to grow layers of gate oxide or gate base materials of different thicknesses for dual gate structures. The process starts with a semiconductor surface in which STI regions have been formed and over the surface of which a layer of gate base material has been grown. A dielectric, such as nitride, is deposited, masked and etched over a first region where thin gate base material must be created thereby exposing the surface of the deposited layer of gate base material in that region. The gate base material is etched to the desired thickness, creating a first thin layer of gate base material. A thick first layer of gate electrode material, poly, is deposited over the dielectric thereby including the surface of the first thin layer of gate base material, and polished down to the surface of the dielectric leaving gate electrode material deposited in the opening above the first thin layer of gate base material. The process creates over a second region of the gate base material a gate electrode having a second thickness of the gate base material. The dielectric is removed leaving gate electrode structures in place above thin layers of gate base materials, the latter being of differe…