Gate technology for strained surface channel and strained buried channel MOSFET devices
US6583015B2 · kind B2 · utility
100Cited by
14References
25Claims
0Family size
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Key dates
| Filing date | Aug 6, 2001 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Aug 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.