Memory integrated circuit with improved reliability
US6584009B1 · kind B1 · utility
5Cited by
3References
15Claims
0Family size
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Inventors
Key dates
| Filing date | Mar 21, 2002 |
| Grant date | Jun 24, 2003 |
| Priority date | — |
| Expiry date | Mar 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.