Method of forming dual-metal gates in semiconductor device
US6586288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Nov 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove, and forming a second metal gate in the second groove by etching the second metal layer and second gate insulating lay…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.