Spacer assisted trench top isolation for vertical DRAM's

US6586300B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Klaus Hummler · Apex, US
• Arnd Scholz · Poughkeepsie, US

Key dates

• Filing date: Apr 18, 2002
• Grant date: Jul 1, 2003
• Expiry date: Apr 18, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/047

Abstract

A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133). The TTI layer (148) comprises the first and second insulating layer portions (146/144) that are left remaining over the trench capacitors (118). The TTI layer (148) has a greater thickness over the trench capacitor inner regions (152) than over the trench capa…