Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices
US6586349B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2002 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for fabricating a semiconductor device, and to a semiconductor device, the method including providing a semiconductor substrate; depositing on the semiconductor substrate a composite dielectric material layer including elements of at least two dielectric materials, in which the step of depositing includes providing a first precursor for a first dielectric material at a first rate and providing a second precursor for a second dielectric material at a second rate, in which at least a portion of the at least two dielectric materials are deposited simultaneously. The semiconductor device includes a composite dielectric material layer having a thickness, and including elements of a first dielectric material and a second dielectric material, in which the composite dielectric material layer includes a varying concentration ratio of the first dielectric material to the second dielectric material through the thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.