Partitionable embedded circuit test system for integrated circuit
US6587979B1 · kind B1 · utility
65Cited by
24References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jan 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.