Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling
US6587982B1 · kind B1 · utility
7Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Nov 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.