Stacked semiconductor package formed on a substrate and method for fabrication
US6590282B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Apr 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01078
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor package formed on a substrate arranged in a serpentine configuration and a method for such fabrication are disclosed. The package is formed by at least one substrate section formed on the substrate bonded to at least one IC die by a flip-chip bonding method. The substrate is then folded onto itself such that the backside of a first IC die is adhesively bonded to the backside of a second IC die. A heat sink may optionally be utilized in-between the IC dies during the adhesive bonding process to further enhance thermal dissipation. The substrate section may be bonded to a printed circuit board by a plurality of solder balls formed on an active surface of the substrate section. The present invention can be bonded to a printed circuit board either in a horizontal position or in a vertical position for saving more real-estate on the board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.