6F2 DRAM array with apparatus for stress testing an isolation gate and method
US6590817B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Aug 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes a 6F2 DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and second memory cells. The isolation gate is configured to provide electrical isolation between the first and second memory cells. The DRAM also includes a first switch having first and second load electrodes and a control electrode configured to accept a first control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to ground. The DRAM additionally includes a second switch having first and second load electrodes and a control electrode configured to accept a second control signal. The first load electrode is coupled to the isolation gate and the second load electrode is coupled to a stress voltage source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.