Three-dimensional memory array and method for storing data bits and ECC bits therein
US6591394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Mar 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B99/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory array and method for storing data bits and ECC bits therein is provided. A three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is described. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.