Method and apparatus for interconnect-driven optimization of integrated circuit design
US6591407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Mar 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.