Current source and drain arrangement for magnetoresistive memories (MRAMs)

US6594176B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Stefan Lammers · Hersbruck, DE

Key dates

• Filing date: Jun 20, 2001
• Grant date: Jul 15, 2003
• Expiry date: Jun 20, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/943
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An MRAM device (400) having write paths with substantially uniform length and resistance for all memory cells within the memory array (411). CVC circuits are positioned with respect to the memory array (411) such that the write path length along conductive lines of the MRAM device (401) is substantially the same for all memory cells in the array (411), ensuring that the resistance along the write path is substantially uniform, and therefore, the amount of write current provided by the CVC circuits to write the cells of the memory array (411) is substantially the same.