Fault emulation testing of programmable logic devices
US6594610B1 · kind B1 · utility
22Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2001 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Sep 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.