Method and apparatus for providing optimized access to circuits for debug, programming, and test
US6594802B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Feb 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31705
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An access interface for accessing electrical nodes of an electronic circuit for programming, testing, and debugging the electronic circuit. The access interface includes a protocol generator and a data generator that may be programmed to apply control and/or data sequences directly to the electronic circuit. The access interface performs operational commands based upon a plurality of states included in a programmable state machine. By suitably programming the protocol generator, the data generator, and the state machine, electrical nodes of the electronic circuit can be accessed in reduced time using a reduced number of operations. The access interface is controlled by a test resource apparatus, which communicates with the electronic circuit connected to the access interface. The access interface may be implemented as a downloadable circuit, e.g., it may be programmed into a programmable logic device by the test resource apparatus. Alternatively, the access interface may be implemented as a fixed/permanent circuit in an ASIC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.