Process for forming multi-layer electronic structures
US6594891B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49149
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process of forming a multi-layer electronic composite structure. The process includes providing at least one core including at least one plane of at least one electrically conducting material with a plane of at least one electrically insulating material on both sides of the at least one plane of at least one electrically conducting material. The at least one core includes a plurality of placed through holes formed therethrough. At least one pad is provided over at least one of the plated through holes. The pad provides a flat surface for attaching an electronic device and also prevents solder from entering the at least one plated through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.