Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug

US6596563B2 · kind B2 · utility

Assignee

• Sun Microsystems Inc. · US

Inventors

• Xuejun Yuan · San Jose, US
• Xiaowei Jin · Palatine, US
• Rambabu Pyapali · Cupertino, US
• Raymond A. Heald · Los Altos, US
• James M. Kaku · Palo Alto, US
• Helen Dunn · San Jose, US
• Thelma C. Taylor · San Jose, US
• Peter Lai · San Jose, US
• Aharon Ostrer · Herzliya, IL

Key dates

• Filing date: Mar 4, 2002
• Grant date: Jul 22, 2003
• Expiry date: Mar 4, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design.In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.