Monitoring error conditions in an integrated circuit
US6598177B1 · kind B1 · utility
28Cited by
65References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31705
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention relates to monitoring error conditions in an integrated circuit. The integrated circuit has a packet router to which a plurality of functional modules are connected between which packets are transmitted. Each functional module is associated with an error monitoring register for monitoring error conditions. The error monitoring register contains a plurality of error flags which can be set when a particular error condition is detected. The invention particularly but not exclusively relates to the setting of communication error flags relating to errors in communication of the packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.