CMOS with strained silicon channel NMOS and silicon germanium channel PMOS

US6600170B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventor

• Qi Xiang · San Jose, US

Key dates

• Filing date: Dec 17, 2001
• Grant date: Jul 29, 2003
• Expiry date: Dec 17, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.