Patent · US Expired

MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors

US6600200B1 · kind B1 · utility

124Cited by

5References

4Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Bernhard Lustig · Munich, DE
Herbert Schafer · Höhenkirchen-Siegertsbrunn, DE
Lothar Risch · Neubiberg, DE

Key dates

Filing date	Aug 25, 2000
Grant date	Jul 29, 2003
Priority date	—
Expiry date	Aug 25, 2020

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0167
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.