Method to descramble the data mapping in memory circuits

US6601205B1 · kind B1 · utility

Assignees

• Infineon Technologies AG · DE
• International Business Machines Corporation · US

Inventors

• Gunther Lehmann · Poughkeepsie, US
• Gerd Frankowsky · Wappingers Falls, US
• Louis L. Hsu · Fishkill, US
• Armin Reith · Wappingers Falls, US

Key dates

• Filing date: Sep 29, 2000
• Grant date: Jul 29, 2003
• Expiry date: Oct 15, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31926
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.