Method for fabricating semiconductor devices
US6602787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2001 |
| Grant date | Aug 5, 2003 |
| Priority date | — |
| Expiry date | Jun 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.