Pitch reduction using a set of offset masks
US6605541B1 · kind B1 · utility
53Cited by
5References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 7, 1998 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Jan 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having features with a dimension of ½the minimum pitch wherein the minimum pitch is determined by the parameters of the manufacturing process being used to manufacture the semiconductor device. A target layer of material to be etched with dimensions of ½the minimum pitch is first etched with masks having a dimension of the minimum pitch and the target layer of material is then etched with the masks offset by ½the minimum pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.