Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance
US6605551B2 · kind B2 · utility
44Cited by
5References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2000 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Dec 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/135
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate, using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.