Multiprocessor speculation mechanism with imprecise recycling of storage operations
US6606702B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2000 |
| Grant date | Aug 12, 2003 |
| Priority date | — |
| Expiry date | Nov 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled. An instruction sequence, which includes a barrier instruction and a load instruction that follows the barrier instruction in program order, is received for execution. In response to the barrier instruction, a barrier operation is issued on an interconnect. Following, in response to the load instruction and while the barrier operation is pending, a load request is issued to memory. When a pre-determined type of invalidate, which is affiliated with the load request, is received before the receipt of an acknowledgment for the barrier operation, data that is returned by memory in response to the load request is discarded and the load request is re-issued. The pre-determined type of invalidate includes, for example, a snoop invalidate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.