Programmable resistance memory array
US6608773B2 · kind B2 · utility
51Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2001 |
| Grant date | Aug 19, 2003 |
| Priority date | — |
| Expiry date | Oct 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system, comprising: a memory cell comprising a programmable resistance element programmable to at least a first resistance state and a second resistance state. The memory cell interconnecting a row line and a column line. A power line, distinct from the row line and the column line, coupling said memory cell to a power source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.